Everspin Technologies has announced a comprehensive design guide to streamline the integration of its 1Gb Spin-transfer Torque Magnetoresistive Random Access Memory (STT-MRAM) product in the storage marketplace. Xilinx has been supporting Everspins STT-MRAM for two generations and enables the 1Gb STT-MRAM solution using its DDR4 controller in the Xilinx Vivado development environment. The integrated solution provides a number of benefits, with the design guide and tools structured to address: Timing: Reducing operating frequency, increasing row access timing, increasing counter widths and reducing CAS page sizes.

Power-Up: Enabling anti-scribble mode during calibration. Power-Down: Scramming or moving all relevant data into the persistent memory array. Performance: Increasing pipeline depth and data transfer efficiency.

Scripts: Providing Verilog models and other detailed information to get storage OEMs design up and running effectively. MRAM and persistent memory is an increasingly important technology across a broad range of solutions, said Jamon Bowen, Planning and Storage Segment Director, Data Center Group, Xilinx. Its exciting to see partners make it easy for customers to develop world-class memory sub-systems leveraging the Xilinx platform.

Everspins STT-MRAM devices allow enterprise infrastructure and data centre providers to increase the reliability and performance of systems where high-performance data persistence is critical. This is achieved by delivering protection against power loss without the use of supercapacitors or batteries. In addition, the larger density 1Gb part offers more effective management of I/O streams, creating a greater level of latency determinism and allowing storage OEMs to significantly improve quality of service of their products.

Similar benefits can also be achieved using the 1Gb STT-MRAM device as a persistent data write buffer in storage and fabric accelerators, computational storage, and other applications.