SEALSQ Corp. announced that the launch of its new range of Quantum Resistant, or Post Quantum Secure Chips, the QS7001 and QVault TPM, is planned for as early as fourth quarter of 2024. The Company?s investments and focus on the QUASARs post-quantum project have enabled the engineering team to progress rapidly on the development roadmap.

Following the design phase and production and test of the first proof-of-concept, the QS7001 engineering samples are being produced and expected to be ready to order as soon as the fourth quarter of this year, while the TPM version should be ready by end of year. The upcoming secure chips family is based on a RISC-V Quantum Resistant and CCEAL5+ hardware platform offering CC EAL 5+ certified security and optimized for Kyber and Dilithium quantum resistant algorithms to face the latest quantum attack scenarios. The QS7001 is delivered open for the customer to develop and load their own firmware, while the QVault TPM features a pre-provisioned FIPS 140-3 and TCG certified Trusted Platform Module stack.

SEALSQ has also initiated a strategic move to leverage on the new chip?s powerful hardware architecture capabilities by approaching several large electronic manufacturers to discuss the development of custom quantum resistant chips derived from the QS7001 and integrating application specific customer requirements. By entering the segment of post-quantum ASICs, the company is taking a strategic step in its commercial and industrial strategy, paving the way for a significant new pipeline of business opportunities and revenues. From a financial point of view, ASICs development contracts typically feature customer coverage of Non-Recurring Expenses corresponding to engineering development fees.

From an industrial perspective, this initiative is particularly aligned with SEALSQ?s current project to build a Semiconductor Design and Personalization center, from which engineering resources will fuel the company?s upcoming ASICs activity.