Etron Technology, Inc. will demonstrate interoperability of the Lattice EPC5 FPGA solution and Etron RPC DRAM, laying the groundwork for a miniaturized Endpoint AI subsystem suitable for high volume, form factor constrained applications, at the Etron booth during CES 2019. The high performance, small footprint of the Lattice ECP5 FPGA is complemented by the high bandwidth of the RPC DRAM in its low pin-count miniaturized Wafer Level Chip Scale Package ("WLCSP"), which uses less than half the signals of conventional DDR solutions. The pin-count savings from the revolutionary RPC Architecture is exploited by reduced FPGA resource demands for the memory interface. Benefits are smaller component footprints on a smaller PCB assembly: and with the key elements produced at a lower manufacturing cost.