HSINCHU,
“We expect
“We are excited to collaborate with SKT by providing our processor AX25 to be a key component of SKT’s deep learning SoCs,” said Andes President Frankwell Lin. “The growing intelligent devices call for SoCs with ever more complex computing capabilities. To meet the increasing demands from customers, all Andes V5 processors support RISC-V ratified spec and thus fully benefit from expanding RISC-V ecosystem; in addition, they come with extensive configurable features for embedded applications and user-friendly software development environment.” For example, Andes supports vector interrupt and unaligned access for better performance efficiency and novel features such as PowerBrake, QuickNap™ for additional power saving; StackSafe™ for stack overflow/underflow protection; and CoDense™ for additional code density enhancement on top of RISC-V C-extension.
AndesCore AX25 is equipped with RISC-V P-extension (RVP) ISA to efficiently manipulate multiple data sets simultaneously in one instruction and assist various AI computations. It is also perfect for control-oriented tasks with features such as dynamic branch prediction, instruction/data caches and local memories for low-latency accesses. ECC soft error protection is also supported. Complementing the hardware is AndeSight™, a feature-rich and intuitive integrated development environment. Furthermore, Andes Custom Extension™ (ACE) is a powerful framework to enable custom instruction design to realize domain specific acceleration with high degree of programmability within a reduced development time.
About
Fifteen years in business and a Founding Premier member of
+886-35726533Hsiao-Ling Lin hllin@andestech.com
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